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10-bit, 40/65/80/105 msps 3 v dual analog-to-digital converter ad9218 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features dual 10-bit, 40 msps, 65 msps, 80 msps, and 105 msps adc low power: 275 mw at 105 msps per channel on-chip reference and track-and-hold 300 mhz analog bandwidth each channel snr = 57 db @ 41 mhz, encode = 80 msps 1 v p-p or 2 v p-p analog input range each channel 3.0 v single-supply operation (2.7 v to 3.6 v) power-down mode for single-channel operation twos complement or offset binary output mode output data alignment mode pin compatible with the 8-bit ad9288 C75 dbc crosstalk between channels applications battery-powered instruments hand-held scopemeters low cost digital oscilloscopes i and q communications ultrasound equipment functional block diagram 02001-001 ad9218 ref timing encode a / 10 / 10 / 10 / 10 gnd a in a d9 a to d0 a user select no. 1 user select no. 2 data format/ gain d9 b to d0 b a in a a in b a in b ref in a ref in b ref out encode b timing t/h t/h adc adc output register output register v d v dd figure 1. general description the ad9218 is a dual 10-bit monolithic sampling analog-to- digital converter with on-chip track-and-hold circuits. the product is low cost, low power, and is small and easy to use. the ad9218 operates at a 105 msps conversion rate with outstanding dynamic performance over its full operating range. each channel can be operated independently. the adc requires only a single 3.0 v (2.7 v to 3.6 v) power supply and a clock for full operation. no external reference or driver components are required for many applications. the digital outputs are ttl/cmos compatible and a separate output power supply pin supports interfacing with 3.3 v or 2.5 v logic. the clock input is ttl/cmos compatible and the 10-bit digital outputs can be operated from 3.0 v (2.5 v to 3.6 v) supplies. user-selectable options offer a combination of power-down modes, digital data formats, and digital data timing schemes. in power-down mode, the digital outputs are driven to a high impedance state. product highlights 1. low power. only 275 mw power dissipation per channel at 105 msps. other speed grades proportionally scaled down while maintaining high ac performance. 2. pin compatibility upgrade. allows easy migration from 8-bit to 10-bit devices. pin compatible with the 8-bit ad9288 dual adc. 3. easy to use. on-chip reference and user controls provide flexibility in system design. 4. high performance. maintains 54 db snr at 105 msps with a nyquist input. 5. channel crosstalk. very low at C75 dbc. 6. fabricated on an advanced cmos process. available in a 48-lead low profile quad flat package (7 mm 7 mm lqfp) specified over the industrial temperature range (?40c to +85c).
ad9218* product page quick links last content update: 09/27/2017 comparable parts view a parametric search of comparable parts. documentation application notes ? an-282: fundamentals of sampled data systems ? an-345: grounding for low-and-high-frequency circuits ? an-501: aperture uncertainty and adc system performance ? an-715: a first approach to ibis models: what they are and how they are generated ? an-737: how adisimadc models an adc ? an-741: little known characteristics of phase noise ? an-756: sampled systems and the effects of clock phase noise and jitter ? an-835: understanding high speed adc testing and evaluation ? an-905: visual analog converter evaluation tool version 1.0 user manual ? an-935: designing an adc transformer-coupled front end data sheet ? ad9218: 10-bit, 40/65/80/105 msps 3 v dual analog-to- digital converter data sheet tools and simulations ? visual analog ? ad9218 ibis models reference materials technical articles ? correlating high-speed adc performance to multicarrier 3g requirements ? dnl and some of its effects on converter performance ? ms-2210: designing power supplies for high speed adc ? single chip realizes direct-conversion rx design resources ? ad9218 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad9218 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad9218 rev. c | page 2 of 28 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 dc specifications ......................................................................... 3 digital specifications ................................................................... 4 ac specifications.......................................................................... 5 switching specifications .............................................................. 6 timing diagrams.......................................................................... 6 absolute maximum ratings............................................................ 8 explanation of test levels ........................................................... 8 esd caution.................................................................................. 8 pin configuration and function descriptions............................. 9 terminology .................................................................................... 10 equivalent circuits ......................................................................... 12 typical performance characteristics ........................................... 13 theory of operation ...................................................................... 18 using the ad9218 encode input......................................... 18 digital outputs ........................................................................... 18 analog input ............................................................................... 18 voltage reference ....................................................................... 19 timing ......................................................................................... 19 user select options.................................................................... 19 application information ........................................................... 19 ad9218/ad9288 customer pcb bom...................................... 20 evaluation board ............................................................................ 21 power connector........................................................................ 21 analog inputs ............................................................................. 21 voltage reference ....................................................................... 21 clocking....................................................................................... 21 data outputs............................................................................... 21 data format/gain ...................................................................... 21 timing ......................................................................................... 21 troubleshooting.......................................................................... 21 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 12/06rev. b to rev. c updated format..................................................................universal changes to dc specifications......................................................... 3 1/04rev. a. to rev. b updated format ...................................................................universal changes to general description .................................................... 1 changes to dc specifications......................................................... 3 changes to switching specifications.............................................. 6 added ad9218/ad9288 customer pcb bom section ........... 20 added evaluation board section .................................................. 21 7/03rev. 0 to rev. a updated ordering guide................................................................. 6 changes to terminology section ................................................... .8 changes to figure 17b.................................................................... 19 updated outline dimensions ....................................................... 24
ad9218 rev. c | page 3 of 28 specifications dc specifications v dd = 3.0 v, v d = 3.0 v; external reference, unless otherwise noted. table 1. ad9218bst-40/-65 ad9218bst-80/-105 parameter temp test level min typ max min typ max unit resolution 10 10 bits accuracy no missing codes 1 full vi guaranteed, not tested guaranteed, not tested offset error 2 25c i C18 2 18 C18 2 18 lsb gain error 2 25c i C2 3 8 C2 3.5 8 % fs differential nonlinearity (dnl) 25c i C1 0.3/0.6 1/1.3 C1 0.5/0.8 1.2/1.7 lsb full vi 0.8 0.6/0.9 lsb integral nonlinearity (inl) 25c i C1/C1.6 0.3/1 1/1.6 C1.35/C2.7 0.75/2 +1.35/2.7 lsb full vi 1 1/2.3 lsb temperature drift offset error full v 10 4 ppm/c gain error 2 full v 80 100 ppm/c reference full v 40 40 ppm/c reference internal reference voltage 25c i 1.18 1.24 1.28 1.18 1.24 1.28 v (ref out ) input resistance (ref in a, ref in b) full vi 9 11 13 9 11 13 k analog inputs differential input voltage range (a in, a in ) 3 full v 1 or 2 1 v common-mode voltage 3 full v v d /3 v d /3 v input resistance full vi 8 10 14 8 10 14 k input capacitance 25c v 3 3 pf power supply v d full iv 2.7 3 3.6 2.7 3 3.6 v v dd full iv 2.7 3 3.6 2.7 3 3.6 v supply currents iv d (v d = 3.0 v) 4 full vi 108/117 113/130 172/183 175/188 ma iv dd (v dd = 3.0 v) 4 25c v 7/11 13/17 ma power dissipation dc 5 full vi 325/350 340/390 515/550 525/565 mw iv d power-down current 6 full vi 20 22 ma power supply rejection ratio 25c i 1 1 mv/v 1 no missing codes across industrial temperature range guaranteed for 40 msps, 65 msps, and 80 msps grades. no missing codes at r oom temperature guaranteed for 105 msps grade. 2 gain error and gain temperature coefficients are based on the adc only (with a fixed 1.25 v external reference) 65 grade in 2 v p-p range, 40, 80, 105 grades in 1 v p-p range. 3 (a in C a in ) = 0.5 v in 1 v range (full scale), (a in C a in ) = 1 v in 2 v range (full scale). the analog inputs self-bias to v d /3. this common-mode voltage can be overdriven externally by a low impedance source by 300 mv (differential drive, gain = 1) or 150 mv (differential drive, gain = 2). 4 ac power dissipation measured with rated enco de and a 10.3 mhz analog input @ 0.5 dbfs, c load = 5 pf. 5 dc power dissipation measured with rated enco de and a dc analog input (outputs static, iv dd = 0). 6 in power-down state, iv dd = 10 a typical (all grades).
ad9218 rev. c | page 4 of 28 digital specifications v dd = 3.0 v, v d = 3.0 v; external reference, unless otherwise noted. table 2. test ad9218bst-40/-65 ad9218bst-80/-105 parameter temp level min typ max min typ max unit digital inputs encode input common mode full v v d /2 v d /2 v encode 1 voltage full vi 2 2 v encode 0 voltage full vi 0.8 0.8 v encode input resistance full vi 1.8 2.0 2.3 1.8 2.0 2.3 k logic 1 voltages1, s2, dfs full vi 2 2 v logic 0 voltages1, s2, dfs full vi 0.8 0.8 v logic 1 currents1 full vi C50 0 50 C50 0 50 a logic 0 currents1 full vi C400 C230 C50 C400 C230 C50 a logic 1 currents2 full vi 50 230 400 50 230 400 a logic 0 currents2 full vi C50 0 50 C50 0 50 a logic 1 currentdfs full vi 30 100 200 30 100 200 a logic 0 currentdfs full vi C400 C230 C50 C400 C230 C50 a input capacitances1, s2, encode inputs 25c v 2 2 pf input capacitance dfs 25c v 4.5 4.5 pf digital outputs logic 1 voltage full vi 2.45 2.45 v logic 0 voltage full vi 0.05 0.05 v output coding twos complement or offset binary twos complement or offset binary
ad9218 rev. c | page 5 of 28 ac specifications v dd = 3.0 v, v d = 3.0 v; external reference, unless otherwise noted. table 3. test ad9218bst-40/-65 ad9218bst-80/-105 parameter temp level min typ max min typ max unit dynamic performance 1 signal-to-noise ratio (snr) (without harmonics) f in = 10.3 mhz 25c i 58/55 59/57 57/53 58/55 db f in = nyquist 2 25c i C/54 59/56 55/52 57/54 db signal-to-noise and distortion (sinad) (with harmonics) f in = 10.3 mhz 25c i 58/54 59/56 56/52 58/53 db f in = nyquist 2 25c i C/53 59/55 55/51 57/53 db effective number of bits f in = 10.3 mhz 25c i 9.4/8.8 9.6/9.1 9.1/8.4 9.4/8.6 bits f in = nyquist 2 25c i C/8.6 9.6/8.9 9/8.3 9.3/8.6 bits second harmonic distortion f in = 10.3 mhz 25c i C72/C66 C89/C77 C69/C60 C77/C68 dbc f in = nyquist 2 25c i C/C63 C89/C72 C65/C57 C76/C66 dbc third harmonic distortion f in = 10.3 mhz 25c i C68/C62 C79/C68 C62/C57 C71/C63 dbc f in = nyquist 2 25c i C/C60 C78/C64 C63/C57 C73/C69 dbc spurious free dynamic range (sfdr) f in = 10.3 mhz 25c i C68/C62 C79/C67 C62/C57 C69/C62 dbc f in = nyquist 2 25c i C/C60 C78/C64 C63/C57 C70/C63 dbc two-tone intermodulation distortion (imd) f in1 = 10 mhz, f in2 = 11 mhz at C7 dbfs 25c v C74/C73 dbc f in1 = 30 mhz, f in2 = 31 mhz at C7 dbfs 25c v C73/C73 C77/C67 dbc analog bandwidth, full power 25c v 300 300 mhz crosstalk 25c v C75 C75 dbc 1 ac specifications based on an analog input voltage of C0.5 dbfs at 10.3 mhz, unless otherwise noted. ac specifications for 40, 80, 105 grades are tested in 1 v p-p range and driven differentially. ac specifications for 65 grade are tested in 2 v p-p range and driven differentially. 2 the 65, 80, and 105 grades are tested close to nyquist for tha t grade: 31 mhz, 39 mhz, and 51 mhz for the 65, 80, and 105 grad es, respectively.
ad9218 rev. c | page 6 of 28 switching specifications v dd = 3.0 v, v = 3.0 v; external reference, unless otherwise noted. d table 4. test ad9218bst-40/-65 ad9218bst-80/-105 parameter temp level min typ max min typ max unit encode input parameters maximum encode rate full vi 40/65 80/105 msps minimum encode rate full iv 20/20 20/20 msps encode pulse width high (t eh ) full iv 7/6 5/3.8 ns encode pulse width low (t el ) full iv 7/6 5/3.8 ns aperture delay (t a ) 25c v 2 2 ns aperture uncertainty (jitter) 25c v 3 3 ps rms digital output parameters output valid time (t v ) full vi 2.5 2.5 ns 1 output propagation delay (t pd ) 1 full vi 4.5 7 4.5 6 ns output rise time (t r ) 25c v 1 1.0 ns output fall time (t f ) 25c v 1.2 1.2 ns out-of-range recovery time 25c v 5 5 ns transient response time 25c v 5 5 ns recovery time from power-down 25c v 10 10 cycles pipeline delay full iv 5 5 cycles 1 t and t v pd are measured from the 1.5 level of the encode input to the 50%/50% levels of the digital outputs swing. the digital output loa d during test is not to exceed an ac load of 5 pf or a dc current of 40 a. rise and fall times are measured from 10% to 90%. timing diagrams 02001-002 1/f s t a t eh t el t pd t v sample n encode a encode b d9 a to d0 a d9 b to d0 b a in a a in b data n ? 5 data n ? 4 data n ? 3 data n ? 2 data n ? 1 data n data n ? 5 data n ? 4 data n ? 3 data n ? 2 data n ? 1 data n sample n + 1 sample n + 5 sample n + 6 sample n + 2 sample n + 3 sample n + 4 figure 2. normal operation, same clock (s1 = 1, s2 = 0) channel timing
ad9218 rev. c | page 7 of 28 02001-003 1/f s t a t eh t el t pd t v sample n encode a encode b d9 a to d0 a d9 b to d0 b a in a a in b data n ? 10 data n ? 8 data n ? 6 data n ? 4 data n ? 2 data n data n + 2 data n ? 9 data n ? 7 data n ? 5 data n ? 3 data n ? 1 data n + 1 sample n + 1 sample n + 2 sample n + 7 sample n + 8 sample n + 3 sample n + 4 sample n + 5 sample n + 6 figure 3. normal operation with two clock sources (s1 = 1, s2 = 0) channel timing 02001-004 1/f s t a t eh t el t pd t v sample n encode a encode b d9 a to d0 a d9 b to d0 b a in a a in b data n ? 10 data n ? 8 data n ? 6 data n ? 4 data n ? 2 data n data n ? 11 data n ? 9 data n ? 7 data n ? 5 data n ? 3 data n ? 1 data n + 1 sample n + 1 sample n + 2 sample n + 7 sample n + 8 sample n + 3 sample n + 4 sample n + 5 sample n + 6 data n + 2 figure 4. data align with two clock sources (s1 = 1, s2 = 1) channel timing
ad9218 rev. c | page 8 of 28 absolute maximum ratings explanation of test levels table 5. parameter rating i. 100% production tested. v d , v 4 v dd ii. 100% production tested at 25c and sample tested at specified temperatures. analog inputs C0.5 v to v d + 0.5 v digital inputs C0.5 v to v + 0.5 v dd ref in inputs C0.5 v to v d + 0.5 v iii. sample tested only. digital output current 20 ma iv. parameter is guaranteed by design and characterization testing. operating temperature C55c to +125c storage temperature C65c to +150c maximum junction temperature 150c v. parameter is a typical value only. maximum case temperature 150c a (measured on a 4-layer board with solid ground plane) 57c/w vi. 100% production tested at 25c; guaranteed by design and characterization testing for industrial temperature range. 100% production tested at temperature extremes for military devices. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6. user select modes s1 s2 power-down and data alignment settings 0 0 power down both channel a and channel b. 0 1 power down channel b only. 1 0 normal operation (data align disabled). 1 1 data align enabled (data from both channels available on rising edge of clock a. channel b data is delayed by a ? clock cycle.) esd caution
ad9218 rev. c | page 9 of 28 pin configuration and fu nction descriptions 0 2001-005 gnd v d enc a v dd gnd d9 a (msb) d8 a d7 a d6 a d5 a d4 a d3 a d2 a v d enc b v dd gnd (msb) d9 b d8 b d7 b d6 b d5 b d4 b d3 b d2 b s1 s2 gnd a in a a in a dfs/gain a in b a in b ref in a ref in b d1 a gnd v dd d1 b d0 a gnd gnd d0 b gnd v d ref out v d v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 ad9218 top view (not to scale) figure 5. pin configuration table 7. pin function descriptions pin number mnemonic description gnd ground. 1, 12, 16, 27, 29, 32, 34, 45 2 a in a analog input for channel a. aa in 3 analog input for channel a (complementary). 4 dfs/gain data format select and analog input gain mode. low = offset binary output available, 1 v p-p supported; high = twos complement output available, 1 v p-p supported; floating = offset binary output available, 2 v p-p supported; set to v = twos complement output available, 2 v p-p supported. ref 5 ref in a reference voltage input for channel a. 6 ref out internal reference voltage. 7 ref in b reference voltage input for channel b. 8 s1 user select no. 1. see table 6 . 9 s2 user select no. 2. see table 6 . 10 ba in analog input for channel b (complementary). 11 a in b analog input for channel b. 13, 30, 31, 48 v d analog supply (3 v). 14 enc b clock input for channel b. 15, 28, 33, 46 v dd digital supply (2.5 v to 3.6 v). 17 to 26 d9 to d0 b b digital output for channel b (d9 = msb). b 35 to 44 d0 a to d9 a digital output for channel a (d9 a = msb). 47 enc a clock input for channel a.
ad9218 rev. c | page 10 of 28 terminology full-scale input power analog bandwidth expressed in dbm. computed using the following equation: the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? 001.0 log10 2 input scalefull scalefull z rms v power aperture delay the delay between the 50% point of the rising edge of the encode command and the instant at which the analog input is sampled. gain error gain error is the difference between the measured and the ideal full-scale input voltage range of the adc. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. harmonic distortion, second the ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dbc. crosstalk coupling onto one channel being driven by a low level signal (C40 dbfs) when the adjacent interfering channel is driven by a full-scale signal. harmonic distortion, third the ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dbc. differential analog input resistance, differential analog input capacitance, differential analog input impedance integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line determined by a least-square curve fit. the real and complex impedances measured at each analog input port. the resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. differential analog input voltage range the peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. peak-to-peak differential is computed by rotating the input phase 180 degrees and again taking the peak measurement. the difference is then computed between both peak measurements. maximum conversion rate the encode rate at which parametric testing is performed. output propagation delay the delay between the 50% level crossing of encode a or encode b and the 50% level crossing of the respective channels output data bit. noise (for any range within the adc) differential nonlinearity ? ? ? ? ? ? ?? = 10 10001.0 dbfs dbc dbm noise signal snrfs zv the deviation of any code width from an ideal 1 lsb step. effective number of bits (enob) where z is the input impedance, fs is the full scale of the device for the frequency in question, snr is the value for the particular input level, and signal is the signal level within the adc reported in db below full scale. this value includes both thermal and quantization noise. the effective number of bits is calculated from the measured snr based on the equation 02.6 76.1 db ? = measured snr enob power supply rejection ratio encode pulse width/duty cycle the ratio of a change in input offset voltage to a change in power supply voltage. pulse width high is the minimum amount of time that the encode pulse should be left in logic 1 state to achieve rated performance; pulse width low is the minimum time encode pulse should be left in low state. see timing implications of changing t ench in text. at a given clock rate, these specifications define an acceptable encode duty cycle.
ad9218 rev. c | page 11 of 28 signal-to-noise and distortion (sinad) the ratio of the rms signal amplitude (set 1 db below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral componen t. the peak spurious component may or may not be a harmonic. reported in dbc (that is, degrades as signal level is lowered) or dbfs (always related back to converter full scale). two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dbc. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. reported in dbc (that is, degrades as signal level is lowered) or in dbfs (always related back to converter full scale). worst other spur the ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonics) reported in dbc. transient resp onse time transient response is defined as the time it takes for the adc to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. out-of-range recovery time out-of-range recovery time is the time it takes for the adc to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale or from 10% below negative full scale to 10% below positive full scale.
ad9218 rev. c | page 12 of 28 equivalent circuits v d ref 10k ? 02001-010 02001-b-006 a in a in v d 40k : 30k : 15k : 40k : 30k : 15k : figure 6. analog input stage figure 10. reference inputs 02001-011 s 2 v d 10k? 02001-007 encode v d 600k ? 2.6k ? 2.6k ? figure 11. s2 input figure 7. encode inputs 02001-008 out v d 02001-012 s1 v d 10k? figure 8. reference output stage figure 12. s1 input 02001-013 dfs/gain v ref v d 15k ? 15k ? v dd dx 40k? 02001-009 figure 9. digita l output stage figure 13. dfs/gain input
ad9218 rev. c | page 13 of 28 typical performance characteristics ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (db) 052.5 02001-014 encode = 105msps a in = 50.1mhz at ?0.5dbfs snr = 53.8db sinad = 53.4db h2 = ?69db h3 = ?65.8db figure 14. fft: fs = 105 msps, a in = 50.1 mhz @ C0.5 dbfs, differential, 1 v p-p input range ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (db) 040 02001-015 encode = 80msps a in = 39mhz at ?0.5dbfs snr = 56.1db sinad = 55.5db h2 = ?71.8db h3 = ?66.2db figure 15. fft: fs = 80 msps, a in = 39 mhz @ C0.5 dbfs, differential, 1 v p-p input range ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (db) 032.5 02001-016 encode = 65msps a in = 30.3mhz at ?0.5dbfs snr = 56.1db sinad = 55.9db sfdr = 72db h2 = ?83.2db h3 = ?79db figure 16. fft: fs = 65 msps, a in = 30.3 mhz @ C0.5 dbfs, differential, 2 v p-p input range ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (db) 020 02001-017 encode = 40msps a in = 19.75mhz at ?0.5dbfs snr = 58.4db sinad = 58.3db h2 = ?87db h3 = ?81db figure 17. fft: fs = 40 msps, a in = 19.75 mhz @ C0.5 dbfs, differential, 1 v p-p input range ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (db) 040 02001-018 encode = 105msps a in = 70mhz at ?0.5dbfs snr = 51.9db sinad = 51.8db h2 = ?70.5db h3 = ?76.3db figure 18. fft: fs = 105 msps a in = 70 mhz @ C0.5 dbfs, differential, 1 v p-p input range ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (db) 032.5 02001-019 encode = 65msps a in = 15mhz at ?0.5dbfs snr = 56.4db sinad = 55.9db h2 = ?73.9db h3 = ?71.7db figure 19. fft: fs = 65 msps, a in = 15 mhz @ C 0.5 dbfs; with ad8138 driving adc inputs, 1 v p-p input range
ad9218 rev. c | page 14 of 28 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (db) 015.5 02001-020 encode = 31msps a in = 8mhz at ?0.5dbfs snr = 59.23db sinad = 59.1db h2 = ?87db h3 = ?81db figure 20. fft: fs = 31 msps, a in = 8 mhz @ C0.5 dbfs, differential, 1 v p-p input range 30 35 40 45 50 55 60 65 70 75 80 (db) 02001-021 0 50 100 150 200 250 a in frequency (mhz) sfdr third second figure 21. harmonic distortion (second and third) and sfdr vs. a in frequency (1 v p-p, fs = 105 msps) 30 35 40 45 50 55 60 65 70 75 80 (db) 02001-022 0 50 100 150 200 250 a in frequency (mhz) sfdr third second figure 22. harmonic distortion (second and third) and sfdr vs. a in frequency (1 v p-p, fs = 80 msps) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (db) 015.5 02001-023 encode = 31msps a in = 8mhz at ?0.5dbfs snr = 59db sinad = 58.8db h2 = ?78.7db h3 = ?72.9db figure 23. fft: fs = 31 msps, a in = 8 mhz @ C0.5 dbfs, differential, with ad8138 driving adc inputs,1 v p-p input range ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (db) 052.5 02001-024 encode = 105msps a in 1 = 30.1mhz at ?7dbfs a in 2 = 31.1mhz at ?7dbfs sfdr = ?67dbfs figure 24. two-tone intermodulation distortion (30.1 mhz and 31.1 mhz; 1 v p-p, fs = 105 msps) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (db) 040 02001-025 encode = 80msps a in 1 = 29.3mhz at ?7dbfs a in 2 = 30.3mhz at ?7dbfs sfdr = ?77dbfs figure 25. two-tone intermodulation distortion (29.3 mhz and 30.3 mhz; 1 v p-p, fs = 80 msps)
ad9218 rev. c | page 15 of 28 10 20 30 40 50 60 (db) 70 80 90 0 20 40 60 80 100 120 140 160 180 a in frequency (mhz) 02001-026 h2 1v h2 2v h3 2v 2v single-ended drive 1v differential drive sfdr 2v sfdr 1v h3 1v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (db) 03 02001-029 2 . 5 encode = 65msps a in 1 = 28.1mhz at ?7dbfs a in 2 = 29.1mhz at ?7dbfs sfdr = ?72.9dbfs figure 29. two-tone intermodulation distortion (28 mhz, 29 mhz; 1 v p-p, fs = 65 msps) figure 26. harmonic distortion (second and third) and sfdr vs. a in frequency (fs = 65 msps) 50 55 60 65 70 75 (db) 80 85 90 30 40 10 20 50 60 70 a in frequency (mhz) 02001-027 sfdr third second ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (db) 02 02001-030 0 encode = 40msps a in 1 = 10mhz at ?7dbfs a in 2 = 11mhz at ?7dbfs sfdr = 74dbc figure 30. two-tone intermodulation distortion (10 mhz, 11 mhz; 1 v p-p, fs = 40 msps) figure 27. harmonic distortion (second and third) and sfdr vs. a in frequency (1 v p-p, fs = 40 msps) 45 50 55 60 65 70 75 (db) 40 60 020 80100120 encode rate (msps) 02001-028 sfdr sinad 45 50 55 60 65 70 75 80 (db) 4030 10 20 05 0 6 0 encode rate (mhz) 02001-031 sfdr snr sinad 7 0 8 0 figure 31. sinad and sfdr vs. encode rate (a figure 28. sinad and sfdr vs. encode rate (a in = 10.3 mhz, 105 msps grade) a in = 10.3 mhz, 65 msps grade) a in = C0.5 dbfs differential, 1 v p-p analog input range ) in = C0.5 dbfs differential, 1 v p-p analog input range
ad9218 rev. c | page 16 of 28 30 35 40 45 50 55 60 65 70 75 (db) 43 12 05 6 encode positive pulsewidth (ns) 02001-032 7 8 sfdr sinad 40 45 50 55 60 65 70 75 (db) 02001-035 02468101214 encode positive pulsewidth (ns) sfdr sinad figure 32. sinad and sfdr vs. encode pulse width high, a in = C0.5 dbfs single-ended, 1 v p-p analog input range 105 msps figure 35. sinad and sfdr vs. encode pulse width high, a in = C0.5 dbfs single-ended, 1 v p-p analog input range 65 msps 80 100 120 140 160 180 200 (ma) 02001-033 0 20 40 60 80 100 120 140 encode clock rate (msps) iv d ? 105 iv d ? 65 ?65/?105 iv dd 0 5 10 15 20 25 30 35 40 45 50 iv dd (ma) 2.0 2.5 3.0 3.5 4.0 4.5 (%) 020 ?40 ?20 40 60 80 temperature (c) 02001-036 gain ?105 gain ?65 figure 36. gain error vs. temperature, a figure 33. iv d and iv dd vs. encode rate (a in = 10.3 mhz, @ C0.5 dbfs), C65 msps/C105 msps grade ci = 5 pf in = 10.3 mhz, C65 msps grade, C105 msps grade, 1 v p-p 52 54 56 58 60 62 (db) 64 66 68 020 ?40 ?20 40 60 80 temperature (c) 02001-037 sfdr ?65 sfdr ?105 snr ?65 snr ?105 sinad ?65 sinad ?105 1.119 1.121 1.123 1.125 1.127 1.129 1.131 (v) 020 ?40 ?20 40 60 80 temperature (c) 02001-034 figure 37. snr, sinad, sfdr vs. temperature, a figure 34. v ref output voltage vs. temperature (i load = 300 a) in = 10.3 mhz, C65 msps grade, C105 msps grade, 1 v p-p
ad9218 rev. c | page 17 of 28 0 10 20 30 40 50 60 70 80 90 (db) ?40 ?30 ?60 ?50 ?20 ?10 0 a in input level (dbfs) 02001-040 sfdr ? dbfs sfdr ? dbc snr ? dbc 70db ref line 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 (v) 02001-038 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 i load (ma) figure 40. sfdr vs. a figure 38. v ref vs. i load ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 (lsb) 1.0 1.5 2.0 02001-039 codes 0 1024 figure 39. typical inl plot, 10.3 mhz a in @ 80 msps in input level, 10.3 mhz a in @ 80 msps ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 (lsb) 02001-041 codes 0 1024 figure 41. typical dnl plot, 10.3 mhz a in @ 80 msps
ad9218 rev. c | page 18 of 28 theory of operation analog input the ad9218 adc architecture is a bit-per-stage pipeline-type converter utilizing switch capacitor techniques. these stages determine the 7 msbs and drive a 3-bit flash. each stage provides sufficient overlap and error correction, allowing optimization of comparator accuracy. the input buffers are differential, and both sets of inputs are internally biased. this allows the most flexible use of ac-coupled or dc-coupled and differential or single-ended input modes. the output staging block aligns the data, carries out the error correction, and feeds the data to output buffers. the set of output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. there is no discernible difference in performance between the two channels. the analog input to the ad9218 is a differential buffer. for best dynamic performance, impedance at a a in and in should match. special care was taken in the design of the analog input section of the ad9218 to prevent damage and data corruption when the input is overdriven. the nominal input range is 1.024 v p-p. optimum performance is obtained when the part is driven differentially where common-mode noise is minimized and even-order harmonics are reduced. figure 42 shows an example of the ad9218 being driven differentially via a wideband rf transformer for ac-coupled applications. as shown in figure 43 , applications that require dc-coupled differential drives can be accommodated using the ad8138 differential output op amp. using the ad9218 encode input 02001-042 ad9218 50 ? analog signal source a in a in 25? 25? 0.1f 1:1 any high speed adc is extremely sensitive to the quality of the sampling clock provided by the user. a track-and-hold circuit is essentially a mixer. any noise, distortion, or timing jitter on the clock is combined with the desired signal at the analog-to- digital output. for that reason, considerable care has been taken in the design of the encode input of the ad9218, and the user is advised to give commensurate thought to the clock source. the encode input is fully ttl/cmos compatible. figure 42. using a wideband transformer to drive the ad9218 02001-043 ad9218 50 ? analog signal source a in a in 10k ? 5k? av dd 0.1f 500? 500? 500 ? 525? ad8138 vocm 15pf 25? 25? digital outputs the digital outputs are ttl/cmos compatible for lower power consumption. during power-down, the output buffers transition to a high impedance state. a data format selection option supports either twos complement (set high) or offset binary output (set low) formats. figure 43. using the ad8138 to drive the ad9218
ad9218 rev. c | page 19 of 28 voltage reference application information a stable and accurate 1.25 v voltage reference is built into the ad9218 (vref out). typically, the internal reference is used by strapping pin 5 (ref the wide analog bandwidth of the ad9218 makes it very attractive for a variety of high performance receiver and encoder applications. a) and pin 7 (ref in in b) to pin 6 (ref figure 44 shows the dual adc in a typical low cost i and q demodulator implementation for cable, satellite, or wireless lan modem receivers. the excellent dynamic performance of the adc at higher analog input frequencies and encode rates lets users employ direct if sampling techniques. if sampling eliminates or simplifies analog mixer and filter stages to reduce total system cost and power. out ). the input range for each channel can be adjusted independently by varying the reference voltage inputs applied to the ad9218. no appreciable degradation in performance occurs when the reference is adjusted 5%. the full-scale range of the adc tracks reference voltage, which changes linearly (a 5% change in vref results in a 5% change in full scale). 02001-044 bpf bpf vco vco if in 90 q adc i adc ad9218 timing the ad9218 provides latched data outputs, with five pipeline delays. data outputs are available one propagation delay (t pd ) after the rising edge of the encode command (see figure 2 through figure 4). the length of the output data lines and loads placed on them should be minimized to reduce transients within the ad9218. these transients can detract from the dynamic performance of the converter. the minimum guaranteed conversion rate is 20 msps. at clock rates below 20 msps, dynamic performance degrades. figure 44. typical i/q demodulation scheme user select options two pins are available for a combination of operational modes, enabling the user to power down both channels, excluding the reference, or just the b channel. both modes place the output buffers in a high impedance state. recovery from a power-down state is accomplished in 10 clock cycles following power-on. the other option allows the user to skew the b channel output data by one-half a clock cycle. in other words, if two clocks are fed to the ad9218 and are 180 degrees out of phase, enabling the data align allows channel b output data to be available at the rising edge of clock a. if the same encode clock is provided to both channels and the data align pin is enabled, output data from channel b is 180 degrees out of phase with respect to channel a. if the same encode clock is provided to both channels and the data align pin is disabled, both outputs are delivered on the same rising edge of the clock.
ad9218 rev. c | page 20 of 28 ad9218/ad9288 customer pcb bom table 8. bill of materials no. qty reference designator device package value comments 1 29 c1, c3 to c15, c20, c21, c24, c25, c27, c30 to c35, c39 to c42 capacitor 0603 0.1 f 2 2 c2, c36 capacitor 0603 15 pf 8138 out 3 7 c16Cc19, c26, c37, c38 capacitor tajd 10 f 4 28 e1, e2, e3, e4, e12 to e30, e34 to e38 w-hole w-hole 5 4 h1, h2, h3, h4 mthole mthole 6 5 j1, j2, j3, j4, j5 sma sma j2, j3 not placed 7 3 p1, p4, p11 4-lead power connector post z5.531.3425.0 wieland 8 3 p1, p4, p11 4-lead power connector detachable connector 25.602.5453.0 wieland 9 1 p2, p3 1 80-lead rt. angle male tsw-140-08- l-d-ra samtec 10 4 r1, r2, r32, r34 resistor 0603 36 r1, r2, r32, r34, not placed 11 9 r3, r7, r11, r14, r22, r23, r24, r30, r51 resistor 0603 50 r11, r22, r23, r24, r30, r51 not placed 12 17 r4, r5, r8, r9, r10, r12, r13, r20, r33, r35, r36, r37, r40, r42, r43, r50, r53 resistor 0603 0 r43, r50 not placed 13 2 r6, r38 resistor 0603 25 r6, r38 not placed 14 6 r15, r16, r18, r26, r29, r31 resistor 0603 500 r16, r29 not placed 15 2 r17, r25 resistor 0603 525 16 2 r19, r27 resistor 0603 4 k 17 12 r21, r28, r39, r41, r44, r46 to r49, r52, r54, r55 resistor 0603 1 k 18 2 t1, t2 transformer adt1-1wt minicircuits 19 1 u1 ad9288 or ad9218 2 lqfp48 20 2 u2, u3 74lcx821 21 2 u5, u6 sn74vcx86 22 4 u7, u8, u9, u10 resistor array cts 47 768203470g 23 2 u11, u12 ad8138 op amp 3 1 p2, p3 are implemented as one physical 80-lead connector samtec tsw-140-08-l-d-ra. 2 ad9288/pcb populated with ad9288-100, ad9218-65/pcb populated with ad9218-65, ad9218-105/pcb populated with ad9218-105. 3 to use optional amp plac e r22, r23, r30, r24, r16, r29, remove r4, r36.
ad9218 rev. c | page 21 of 28 evaluation board the ad9218/ad9288 customer evaluation board offers an easy way to test the ad9218 or the ad9288. the compatible pinout of the two parts facilitates the use of one pcb for testing either part. the pcb requires power supplies, a clock source, and a filtered analog source for most adc testing required. power connector power is supplied to the board via a detachable 12-lead power strip. the minimum 3 v supplies required to run the board are v d , v dl , and v dd . to allow the use of the optional amplifier path, 5 v supplies are required. analog inputs each channel has an independent analog path that uses a wideband transformer to drive the adc differentially from a single-ended sine source at the input smas. the transformer paths can be bypassed to allow the use of a dc-coupled path using two ad8138 op amps with a simple board modification. the analog input should be band-pass filtered to remove any harmonics in the input signal and to minimize aliasing. voltage reference the ad9218 has an internal 1.25 v voltage reference; an external reference for each channel can be employed instead by connecting two external voltage references at the power connector and setting jumpers at e18 and e19. the evaluation board is shipped configured for internal reference mode. clocking each channel can be clocked by a common clock input at sma inputs encode a and encode b. the channels can also be clocked independently by a simple board modification. the clock input should be a low jitter sine source for maximum performance. data outputs the data outputs are latched on board by two 10-bit latches and drive an 8-lead connector, which is compatible with the dual- channel fifo board that is available from analog devices, inc. this board, together with adc analyzer software, can greatly simplify adc testing. data format/gain the dfs/gain pin can be biased for desired operation at the dfs jumper located at the s1, s2 jumpers. timing timing on each channel can be controlled, if needed, on the pcb. clock signals at the latches or the data ready signals that go to the output 80-lead connector can be inverted if required. jumpers also allow for biasing of pin s1 and pin s2 for power- down and timing alignment control. troubleshooting if the board does not seem to be working correctly, try the following: ? ver if y p ower at t he ic pi ns. ? check that all jumpers are in the correct position for the desired mode of operation. ? ver if y t hat v ref is at 1.23 v. ? try running encode clock and analog inputs at low speeds (20 msps/1 mhz) and monitor the lcx821 outputs, dac outputs, and adc outputs for toggling. the ad9218 evaluation board is provided as a design example for customers of analog devices. analog devices makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose.
ad9218 rev. c | page 22 of 28 p6 p5 p7 v dd v d v dl + ++ +++ + c37 10f c38 10f c16 10f c17 10f c18 10f c19 10f c26 10f gnd ?5v +5v v d v dd v dl v ref av ref b v dl v dd gnd v d 1 2 3 4 p1 v ref b v ref a gnd gnd 1 2 3 4 p4 gnd ?5v +5v gnd 1 2 3 4 p11 h3 mthole6 h1 mthole6 h2 mthole6 h4 mthole6 gnd 02001-045 v d enc a v dd gnd d9 a (msb) d8 a d7 a d6 a d5 a d4 a d3 a d2 a c7 0.1f c8 0.1f gnd gnd d1 a d0 a gnd v dd gnd v d gnd v dd gnd d0 b d1 b c4 0.1f gnd c3 0.1f gnd c1 0.1f gnd d2 b d3 b d4 b d5 b d6 b d7 b d8 b (msb) d9 b gnd v dd enc b v d c5 0.1f c6 0.1f gnd gnd gnd ampouta ampoutb ampoutab refout gnd c10 0.1f c9 0.1f c11 0.1f c31 0.1f c14 0.1f r4 0 ? r5 0 ? r33 0 ? c15 0.1f c13 0.1f r35 0 ? r1 36 ? r2 36 ? r36 0 ? r34 36? r32 36? r6 25? gnd gnd gnd gnd gnd r3 50? gnd 1 2 6 5 gnd gnd 34 34 t2 1 2 6 5 j4 gnd ampina ampinb ain a j1 gnd ain b r38 25? r7 50? gnd e17 e18 e1 e19 e27 e30e2 e25 vd vrefa e20 e24 e22 vd e29 gnd e23 e26 vd e28 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 gnd a in a a in a dfs/gain ref in a ref out ref in b s1 s2 a in b a in b gnd 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 v d enc a v dd gnd d9 a d8 a d7 a d6 a d5 a d4 a d3 a d2 a ad9218 u1 v d enc b v dd gnd d9 b d8 b d7 b d6 b d5 b d4 b d3 b d2 b d1 a d0 a gnd v dd gnd v d v d gnd v dd gnd d0 b d1 b gnd c12 0.1f gnd gnd gnd ampoutbb r single-ended r single-ended r37 0 ? c30 0.1f c39 0.1f 2y 6 3a 9 gnd 7 3y 8 1a 1 1b 2 1y 3 2a 4 2b 5 vcc 4b 4a 4y 3b 14 13 12 11 10 e4e3 encxa encxa enca gnd gnd gnd gnd vdl tiea vdl vdl clklata gnd r39 1k? r41 1k? r11 50 ? c40 0.1f j3 gnd encode a vdl r44 1k ? r42 0 ? r43 0 ? c25 0.1f e13 e14 e12 vdl e15 gnd gnd r46 1k ? r47 1k ? r9 0 ? dra r10 0 ? u6 sn74vcx86 **dut clock selec table** **to be direct or buffered** drb r12 0 ? 4b 13 1b 2 vcc 14 1a 1 3y 8 3a 9 3b 10 4y 11 4a 12 gnd 2y 2b 2a 1y 7 6 5 4 3 u5 sn74vcx86 encxb gnd vdl tieb gnd r52 1k ? r54 1k ? r51 51? c42 0.1f j2 gnd encode b encx b enc b r53 0 ? r50 0 ? e36e35 gnd gnd gnd vdl vdl r49 1k ? c41 0.1f vdl e34 e37 e16 vdl e38 gnd gnd r48 1k? r55 1k? clklatb r13 0 ? **dut clock selec table** **to be direct or buffered** j5 gnd r14 50? gnd r20 0 ? r40 0 ? tiea tieb enc a enc b r8 0 ? to tie clocks together gnd ref in b c24 0.1f gnd ref in a c27 0.1f t1 figure 45. pcb schematic
ad9218 rev. c | page 23 of 28 d0m 11 gnd 12 d0x clklata 14 13 +in 8 nc 7 v? 6 ?out 5 ?in vocm v+ +out 1 2 3 4 r17 525 ? r16 500 ? ad8138 ampouta ampoutab u11 ampina r18 500 ? r15 500 ? r19 4k ? r21 1k ? gnd gnd gnd +5v +5v c32 0.1f c33 0.1f r22 50 ? r23 50 ? ?5v c2 15pf +in 8 nc 7 v? 6 ?out 5 ?in vocm v+ +out 1 2 3 4 r25 525 ? r29 500 ? ad8138 ampoutbb ampoutb u12 ampinb r26 500 ? r31 500 ? r27 4k ? r28 1k ? gnd gnd gnd +5v +5v c35 0.1f c34 0.1f r30 50 ? r24 50 ? ?5v c36 15pf opamp input off pin one of transformer d9a 1 d8a 2 d7a 3 d6a 4 d5a 5 d9m d8m d7m d6m d5m 20 19 18 17 16 d4a 6 d3a 7 d2a 8 d1a 9 d0a 10 d4m d3m d2m d1m d0m 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 u7 cts20 value = 50 gnd 1 d9m 2 d8m 3 d7m 4 d6m 5 vdl d9x d8x d7x d6x 24 23 22 21 20 d5m 6 d4m 7 d3m 8 d2m 9 d1m 10 d5x d4x d3x d2x d1x 19 18 17 16 15 oe x0 x1 x2 x3 x4 x5 x6 x7 x8 vcc y0 y1 y2 y3 y4 y5 y6 y7 y8 x9 y9 gnd clk u2 74lcx821 d9x 1 d8x 2 d7x 3 d6x 4 d5x 5 d9p d8p d7p d6p d5p 20 19 18 17 16 d4x 6 d3x 7 d2x 8 d1x 9 d0x 10 d4p d3p d2p d1p d0p 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 u9 cts20 value = 50 p3 header40 40 38 36 34 32 gnd dra gnd d9p d8p 39 37 35 33 31 30 28 26 24 22 d7p d6p d5p d4p d3p 29 27 25 23 21 20 18 16 14 12 d2p d1p d0p gnd gnd 19 17 15 13 11 10 8 6 4 gnd 2 gnd gnd gnd gnd gnd 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 c21 0.1f gnd d9n 11 gnd 12 d9y clklatb 14 13 d0b 1 d1b 2 d2b 3 d3b 4 d4b 5 d0n d1n d2n d3n d4n 20 19 18 17 16 d5b 6 d6b 7 d7b 8 d8b 9 d9b 10 d5n d6n d7n d8n d9n 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 u8 cts20 value = 50 gnd 1 d0n 2 d1n 3 d2n 4 d3n 5 vdl d0y d1y d2y d3y 24 23 22 21 20 d4n 6 d5n 7 d6n 8 d7n 9 d8n 10 d4y d5y d6y d7y d8y 19 18 17 16 15 oe x0 x1 x2 x3 x4 x5 x6 x7 x8 vcc y0 y1 y2 y3 y4 y5 y6 y7 y8 x9 y9 gnd clk u3 74lcx821 d0y 1 d1y 2 d2y 3 d3y 4 d4y 5 d0q d1q d2q d3q d4q 20 19 18 17 16 d5y 6 d6y 7 d7y 8 d8y 9 d9y 10 d5q d6q d7q d8q d9q 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 u10 cts20 value = 50 p2 header40 40 38 36 34 32 gnd drb gnd d9q d8q 39 37 35 33 31 30 28 26 24 22 d7q d6q d5q d4q d3q 29 27 25 23 21 20 18 16 14 12 d2q d1q d0q gnd gnd 19 17 15 13 11 10 8 6 4 gnd 2 gnd gnd gnd gnd gnd 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 c20 0.1f gnd 02001-046 nc = no connect figure 46. pcb schematic (continued)
ad9218 rev. c | page 24 of 28 02001-047 02001-050 figure 47. top silkscreen figure 50. split power plane 02001-048 02001-051 figure 48. top routing figure 51. bottom routing 02001-049 02001-052 figure 49. ground plane figure 52. bottom silkscreen
ad9218 rev. c | page 25 of 28 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706-a figure 53. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters ordering guide model temperature range package description package option ad9218bst-40 C40c to +85c 48-lead low profile quad flat pack (lqfp) st-48 ad9218bst-rl40 C40c to +85c 48-lead low profile quad flat pack (lqfp) st-48 ad9218bstz-40 C40c to +85c 48-lead low profile quad flat pack (lqfp) st-48 1 ad9218bstz-rl40 C40c to +85c 48-lead low profile quad flat pack (lqfp) st-48 1 ad9218bst-65 C40c to +85c 48-lead low profile quad flat pack (lqfp) st-48 ad9218bst-rl65 C40c to +85c 48-lead low profile quad flat pack (lqfp) st-48 ad9218bstz-65 C40c to +85c 48-lead low profile quad flat pack (lqfp) st-48 1 ad9218bstz-rl65 C40c to +85c 48-lead low profile quad flat pack (lqfp) st-48 1 ad9218bst-80 C40c to +85c 48-lead low profile quad flat pack (lqfp) st-48 ad9218bst-rl80 C40c to +85c 48-lead low profile quad flat pack (lqfp) st-48 ad9218bstz-80 C40c to +85c 48-lead low profile quad flat pack (lqfp) st-48 1 ad9218bstz-rl80 C40c to +85c 48-lead low profile quad flat pack (lqfp) st-48 1 ad9218bst-105 C40c to +85c 48-lead low profile quad flat pack (lqfp) st-48 ad9218bst-rl105 C40c to +85c 48-lead low profile quad flat pack (lqfp) st-48 AD9218BSTZ-105 C40c to +85c 48-lead low profile quad flat pack (lqfp) st-48 1 ad9218bstz-rl105 ?40c to +85c 48-lead low profile quad flat pack (lqfp) st-48 1 ad9218-65pcb evaluation board (supports -40/-65 grade) ad9218-105pcb evaluation board (supports -80/-105 grade) 1 z = pb-free part.
ad9218 rev. c | page 26 of 28 notes
ad9218 rev. c | page 27 of 28 notes
ad9218 rev. c | page 28 of 28 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c02001-0-12/06(c)

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